Go to “ultra96v2-vitis-pkg/vivado” that you have created. you can use pwd command to check the folder. And from the popup menu select “Create HDL Wrapper… ” and select the “Let Viviado manage wrapper and auto-update” option in the dialog box.Ģ6- Then under the PROGRAM AND DEBUG option in the left-hand side panel, select “Generate Bitstream” and wait until the end of the process.Ģ7- After generating the bitstream, go to the TCL Console view and make sure you are in the right folder. And from the popup menu select “Generate Output Products…”.Ģ4- Select the Generate button and wait for the process to finish.Ģ5- Again, press the right-click on the “ultra96v2_design (ultra96v2_design.bd)” option in the source view panel. Set_property fault_output_type "sd_card" Ģ2- Press the right-click in Diagram view and in the popup menu select Validate Design.Ģ3- Press the right-click on the “ultra96v2_design (ultra96v2_design.bd)” option in the source view panel. Set_property sign_intent.datacenter false Set_property sign_intent.external_host false Change ids of clk_out2, clk_out3, and clk_out4 to 1, 2, and 3, respectively.Ģ0- In the xlconcat_0 interfaces, enable In0, Int1, Int2, Int3, Int4, Int5, Int6, Int7, which are interrupt interfaces.Ģ1- Go to the “TCL Console” view and run these commands set_property sign_intent.embedded true Note, to change the id filed you must press the Enter key on your keyboard. So, don't forget to press Enter each time.ġ8- Enable the following clock interfaces clk_out1ġ9- Select the enabled clk_out1 and in the Options window change the id to 0 and select the is_default. Note, to change the sptag filed you must press the Enter key on your keyboard. S_AXI_HP3_FPD 17- Select S_AXI_HPC0_FPD port and write HPC0 in the sptag under Option in Platform Interface Properties pannel. (Window–>Platform Interfaces).ġ5- Click on “Enable platform interfaces” if this the first time you select the Platform Interfaces option in the project.ġ6- Right-click on each option and select Enable to enable the following interfaces: M_AXI_HPM0_FPD For this purpose, select “Platform Interfaces” option from the “Window” menu in the Vivado IDE. Figure 16 Figure 17ġ4- Now, we should declare the platform (PFM) interface and properties. Figure 14ġ3- Configure the added IP as Figure 16 and connect that to the Zynq as shown in Figure 7. Figure 13ġ1- Add connections as Figure 14. Figure 12ġ0- Add four Processor System Reset IPs corresponding to the four output clocks. Add four output clocks with different output frequencies, and make sure that the reset type is “Active Low”. Figure 11ĩ- Double click on the added IP and configure that as Figure 12. Figure 9ħ- Double click on the Zynq IP and configure that as Figure 10 Figure 10Ĩ- Add a Clocking Wizard IP to the design. Figure 7ĥ- Add a Zynq UltraScale+ MPSoC IP into the Diagram view Figure 8Ħ- Click on “Run Block Automation” and make sure “Apply Board Reset” is selected. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6Ĥ- In the Vivado project, create a block design with the name of ultra96v2_design. Figures 1-6 show the flow of the project creation. 1- XSA designġ- create a directory called ultra96v2-vitis-pkg mkdir ultra96v2-vitis-pkgĢ- create a director called vivado mkdir vivadoģ- Run Vivado and create a project called ultra96v2-xsa in the ultra96v2-vitis-pkg/vivado folder.
To make Vivado detects the board, copy the Avnet ultra96v2 board definition files (at here) to the /data/boards/board_files.
PETALINUX FAILED TO DOWNLOAD U BOOT.ELF INSTALL
Note that, the Xilinx Vitis software includes Vivado, so you do not need to install that separately. I have installed Xilinx Vitis and Petalinux 2019.2 under the Ubuntu 18.04 OS. In the sequel, I am trying to briefly explain each step. Test– Create a simple application to test the generated platform.Create Platform – Using Xilinx Vitis to generate the Platform.Linux OS – Generating a PetaLinux project to configure Linux.XSA design – Generating a Vivado project containing the underlying hardware.
PETALINUX FAILED TO DOWNLOAD U BOOT.ELF HOW TO
How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.1Ĭreating the Ulra96v2 platform in the Xilinx Vitis has four steps: Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits
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